SPICELib.parts.breakout

SPICELib.parts.breakout.Ground SPICELib.parts.breakout.Rbreak SPICELib.parts.breakout.Cbreak SPICELib.parts.breakout.Lbreak SPICELib.parts.breakout.PSPICE_diode SPICELib.parts.breakout.Spice2MOS1 SPICELib.parts.breakout.Spice2MOS1P

Information




breakout package





The following summary table lists all the device types of breakout package.
Each device type is described in detail in the model documentation.



Table 1. breakout package devices.



Model
Device type



Ground
'0' ground



Rbreak
Resistor



Cbreak
Capacitor



Lbreak
Capacitor



PSPICE_diode
PSPICE diode



Spice2MOS1
SPICE2 level1 n-channel MOSFET



Spice2MOS1P
SPICE2 level1 p-channel MOSFET











NameDescription


Ground
 


Rbreak
 


Cbreak
 


Lbreak
 


PSPICE_diode
 


Spice2MOS1
 


Spice2MOS1P
 








SPICELib.parts.breakout.Ground
SPICELib.parts.breakout.Ground

SPICELib.parts.breakout.Ground

Information





Ground model




Figure 1. Ground.




Node



Table 1. Instantiation of Pin class



Name
Comment


p
(+) node






Table 2. (+) node variables.



Name
Description



p.vDC
Static model.



p.vTran
Large-signal voltage



p.vAC_Re
AC small-signal voltage. Real part.



p.vAC_Im
AC small-signal voltage. Imaginary part.







Parameters


None.




Variables of interest to the library user


None.




Constitutive relations


Table 3. Model formulations.



Static
p.vDC=0


AC small-signal
p.vAC_Re=0
p.vAC_Im=0


Large signal
p.vTran=0









Modelica definition


model Ground 
  extends src.BREAKOUT.Ground;
end Ground;







SPICELib.parts.breakout.Rbreak
SPICELib.parts.breakout.Rbreak

SPICELib.parts.breakout.Rbreak

Information





Rbreak - Linear resistor




Figure 1. Resistor.




Nodes



Table 1. Instantiations of Pin class.



Name
Description


p
(+) node


n
(-) node






(+) and (-) nodes define the polarity when the resistor has a
positive voltage across it. The voltage across the component
is therefore defined as the (+) node voltage minus the
(-) node voltage.


Positive current flows from the (+) node through the resistor
to the (-) node.



Table 2. (+) node variables.



Name
Description



p.vDC
Static model.



p.vTran
Large-signal voltage



p.vAC_Re
AC small-signal voltage. Real part.



p.vAC_Im
AC small-signal voltage. Imaginary part.



pinP_vAC_mag
AC small-signal voltage. Magnitude.



pinP_vAC_mag_dB
AC small-signal voltage. Magnitude (dB).



pinP_vAC_phase
AC small-signal voltage. Phase (deg).






Table 3. (-) node variables.



Name
Description



n.vDC
Static model.



n.vTran
Large-signal voltage



n.vAC_Re
AC small-signal voltage. Real part.



n.vAC_Im
AC small-signal voltage. Imaginary part.



pinN_vAC_mag
AC small-signal voltage. Magnitude.



pinN_vAC_mag_dB
AC small-signal voltage. Magnitude (dB).



pinN_vAC_phase
AC small-signal voltage. Phase (deg).








Parameters



Table 4. Resistor parameters.



Name
Type
Default
Description


R
SI.Resistance
1000
Resistance value


HIDDEN_COMPONENT
Boolean
false
See analyses package documentation.







Variables of interest to the library user




Table 5. Voltage across the resistor.



Name
Description



vDC
Static model.



vTran
Large-signal voltage



vAC_Re
AC small-signal voltage. Real part.



vAC_Im
AC small-signal voltage. Imaginary part.



vAC_mag
AC small-signal voltage. Magnitude.



vAC_mag_dB
AC small-signal voltage. Magnitude (dB).



vAC_phase
AC small-signal voltage. Phase (deg).






Table 6. Current flowing through the resistor.



Name
Description



iDC
DC current.



iTran
Large-signal current.



iAC_Re
Small-signal current. Real part.



iAC_Im
Small-signal current. Imaginary part.



iAC_mag
AC small-signal current. Magnitude.



iAC_mag_dB
Small-signal current. Magnitude (dB).



iAC_phase
Small-signal current. Phase (deg).








Constitutive relations


Table 7. Model formulations.



Static
vDC = R * iDC


AC small-signal
vAC_Re  = R * iAC_Re

vAC_Im = R * iAC_Im


Large signal
vTran = R * iTran









Parameters




NameDefaultDescription


HIDDEN_COMPONENTfalseEnable or disable log


R1000Resistance [Ohm]




Modelica definition


model Rbreak 
  extends src.BREAKOUT.Rbreak;
  
end Rbreak;







SPICELib.parts.breakout.Cbreak
SPICELib.parts.breakout.Cbreak

SPICELib.parts.breakout.Cbreak

Information





Cbreak - Linear capacitor




Figure 1. Capacitor.




Nodes



Table 1. Instantiations of Pin class.



Name
Description


p
(+) node


n
(-) node






(+) and (-) nodes define the polarity when the capacitor has a
positive voltage across it. The voltage across the component
is therefore defined as the (+) node voltage minus the
(-) node voltage.


Positive current flows from the (+) node through the capacitor
to the (-) node.



Table 2. (+) node variables.



Name
Description



p.vDC
Static model.



p.vTran
Large-signal voltage



p.vAC_Re
AC small-signal voltage. Real part.



p.vAC_Im
AC small-signal voltage. Imaginary part.







Table 3. (-) node variables.



Name
Description



n.vDC
Static model.



n.vTran
Large-signal voltage



n.vAC_Re
AC small-signal voltage. Real part.



n.vAC_Im
AC small-signal voltage. Imaginary part.








Parameters



Table 4. Capacitor parameters.



Name
Type
Default
Description


C
SI.Capacitance
1e-9
Capacitance value


IC
SI.Voltage
0
Initial voltage across the capacitor during the bias point 
calculation (see analyses.OP model documentation).

Note: the initial voltage across the capacitor can also be set
by using the IC1 part if the capacitor is connected to ground
or by using the IC2 part for setting the initial conditions
between two nodes (these parts can be found in special
package). 


IC_ENABLED
Boolean
false
The capacitor parameter IC_ENABLED enables or disables
the IC property. It allows distinguishing between the cases
when IC is intentionally set to zero and those cases when the
IC property is not enabled.







Variables of interest to the library user




Table 5. Voltage across the capacitor.



Name
Description



vDC
Static model.



vTran
Large-signal voltage



vAC_Re
AC small-signal voltage. Real part.



vAC_Im
AC small-signal voltage. Imaginary part.







Table 6. Current flowing through the capacitor.



Name
Description



iDC
DC current.



iTran
Large-signal current.



iAC_Re
Small-signal current. Real part.



iAC_Im
Small-signal current. Imaginary part.







Table 7. Global variables.



Name
Description



freq
AC small-signal frequency.







Constitutive relations


Table 8. Model formulations.



Static
iDC = 0


AC small-signal
vAC_Re =  iAC_Im / 2 * pi * freq * C

vAC_Im = - iAC_Re / 2 * pi * freq * C


Large signal
C * der(vTran) = iTran











Parameters




NameDefaultDescription


C1E-9Capacitance [F]


IC_ENABLEDfalseIC enabled


IC0Initial voltage [V]




Modelica definition


model Cbreak 
  
  extends src.BREAKOUT.Cbreak;
  
end Cbreak;







SPICELib.parts.breakout.Lbreak
SPICELib.parts.breakout.Lbreak

SPICELib.parts.breakout.Lbreak

Information





Lbreak - Linear inductor




Figure 1. Inductor.




Nodes



Table 1. Instantiations of Pin class.



Name
Description


p
(+) node


n
(-) node






(+) and (-) nodes define the polarity when the inductor has a
positive voltage across it. The voltage across the component
is therefore defined as the (+) node voltage minus the
(-) node voltage.


Positive current flows from the (+) node through the inductor
to the (-) node.



Table 2. (+) node variables.



Name
Description



p.vDC
Static model.



p.vTran
Large-signal voltage



p.vAC_Re
AC small-signal voltage. Real part.



p.vAC_Im
AC small-signal voltage. Imaginary part.







Table 3. (-) node variables.



Name
Description



n.vDC
Static model.



n.vTran
Large-signal voltage



n.vAC_Re
AC small-signal voltage. Real part.



n.vAC_Im
AC small-signal voltage. Imaginary part.








Parameters



Table 4. Inductor parameters.



Name
Type
Default
Description


L
SI.Inductance
1e-9
Inductance value


IC
SI.Current
0
Initial current across the inductor during the bias point 
calculation (see analyses.OP model documentation).




IC_ENABLED
Boolean
false
The inductor parameter IC_ENABLED enables or disables
the IC property. It allows distinguishing between the cases
when IC is intentionally set to zero and those cases when the
IC property is not enabled.







Variables of interest to the library user




Table 5. Voltage across the inductor.



Name
Description



vDC
Static model.



vTran
Large-signal voltage



vAC_Re
AC small-signal voltage. Real part.



vAC_Im
AC small-signal voltage. Imaginary part.







Table 6. Current flowing through the inductor.



Name
Description



iDC
DC current.



iTran
Large-signal current.



iAC_Re
Small-signal current. Real part.



iAC_Im
Small-signal current. Imaginary part.







Table 7. Global variables.



Name
Description



freq
AC small-signal frequency.







Constitutive relations


Table 8. Model formulations.



Static
vDC = 0


AC small-signal
vAC_Re =  iAC_Im * 2 * pi * freq * L

vAC_Im = - iAC_Re * 2 * pi * freq * L


Large signal
L * der(iTran) = vTran











Parameters




NameDefaultDescription


IC0Initial current [V]


IC_ENABLEDfalseIC enabled


L1E-5Inductance [H]




Modelica definition


model Lbreak 
  
  extends src.BREAKOUT.Lbreak;
end Lbreak;







SPICELib.parts.breakout.PSPICE_diode
SPICELib.parts.breakout.PSPICE_diode

SPICELib.parts.breakout.PSPICE_diode

Information





PSPICE_diode - Pspice diode




Figure 1. Diode.




Nodes



Table 1. Instantiations of Pin class.



Name
Description


p
(+) node


n
(-) node






(+) and (-) nodes define the polarity when the diode has a
positive voltage across it. The voltage across the component
is therefore defined as the (+) node voltage minus the
(-) node voltage.


Positive current flows from the (+) node through the diode
to the (-) node.



Table 2. (+) node variables.



Name
Description



p.vDC
Static model.



p.vTran
Large-signal voltage



p.vAC_Re
AC small-signal voltage. Real part.



p.vAC_Im
AC small-signal voltage. Imaginary part.







Table 3. (-) node variables.



Name
Description



n.vDC
Static model.



n.vTran
Large-signal voltage



n.vAC_Re
AC small-signal voltage. Real part.



n.vAC_Im
AC small-signal voltage. Imaginary part.








Parameters



Table 4. Diode parameters.



Name
Type
Default
Description


IS
SI.Current
1e-14
Saturation current.




RS
SI.Resistance
10
Ohmic Resistance.


N
Real
1
Emission coefficient.


TT
SI.Time
0
Transit time.


CJ0
SI.Capacitance
1e-6
Zero-bias junction capacitance.


VJ
SI.Voltage
1
Junction potential.


M
Real
0.5
Grading coefficient.


FC
Real
0.5
Coefficient for forward-bias depletion capacitance formula.


BV
SI.Voltage
1e40
Reverse breakdown voltage (positive number).


IKF
SI.Current
-1
High injection knee current.


ISR
SI.Current
1e-14
Recombination current.


NR
Real
1
Emission coefficient for ISR.


IBV
SI.Current
1e-3
Reverse breakdown current (positive number).







Variables of interest to the library user




Table 5. Voltage across the diode.



Name
Description



vDC
Static model.



vTran
Large-signal voltage



vAC_Re
AC small-signal voltage. Real part.



vAC_Im
AC small-signal voltage. Imaginary part.







Table 6. Current flowing through the diode.



Name
Description



iDC
DC current.



iTran
Large-signal current.



iAC_Re
Small-signal current. Real part.



iAC_Im
Small-signal current. Imaginary part.







Table 7. Global variables.



Name
Description


scaleGMIN
Scale factor of the GMIN stepping algorithm for bias point calculation.


GMIN
Conductance in parallel with the pn junction.


freq
AC small-signal frequency.







References


Massobrio, G. and Antognetti, P. (1993): Semiconductor Device Modeling with SPICE.
McGraw-Hill, Inc.

Model's equations can be found in src package documentation.






Parameters




NameDefaultDescription


HIDDEN_COMPONENTfalseEnable or disable log


IS1e-14Saturation current [A]


RS10Ohmic Resistance [Ohm]


N1Emission coefficient


TT0Transit time [s]


CJ01e-6zero-bias junction capacitance [F]


VJ1Junction potential [V]


M0.5grading coefficient


FC0.5Coefficient for forward-bias depletion capacitance formula


BV1e40reverse breakdown voltage (positive number) [V]


IKF-1High injection knee current [A]


ISR1e-14Recombination current [A]


NR1Emission coefficient for ISR


IBV1e-3Reverse breakdown current (positive number) [A]




Modelica definition


model PSPICE_diode 
  extends src.BREAKOUT.PSPICE_diode;
end PSPICE_diode;







SPICELib.parts.breakout.Spice2MOS1
SPICELib.parts.breakout.Spice2MOS1

SPICELib.parts.breakout.Spice2MOS1

Information





Spice2MOS1 - SPICE2 Level1 n-channel MOSFET




Figure 1. n-channel MOSFET.




Nodes



Table 1. Instantiations of Pin class.



Name
Description


d
drain node


s
source node


g
gate node


b
bulk node







Table 2. drain node variables.



Name
Description



d.vDC
Static model.



d.vTran
Large-signal voltage.



d.vAC_Re
AC small-signal voltage. Real part.



d.vAC_Im
AC small-signal voltage. Imaginary part.







Table 3. (-) source node variables.



Name
Description



s.vDC
Static model.



s.vTran
Large-signal voltage.



s.vAC_Re
AC small-signal voltage. Real part.



s.vAC_Im
AC small-signal voltage. Imaginary part.







Table 4. (-) gate node variables.



Name
Description



g.vDC
Static model.



g.vTran
Large-signal voltage.



g.vAC_Re
AC small-signal voltage. Real part.



g.vAC_Im
AC small-signal voltage. Imaginary part.






Table 5. (-) bulk node variables.



Name
Description



b.vDC
Static model.



b.vTran
Large-signal voltage.



b.vAC_Re
AC small-signal voltage. Real part.



b.vAC_Im
AC small-signal voltage. Imaginary part.








Parameters



Table 6. p-channel MOSFET parameters.



Name
Type
Default
Description


AD
SI.Area
1e-8
Drain junction area.


AS
SI.Area
1e-8
Source junction area.


CGB0
Real
2e-10
Gate-bulk overlap capacitance perimeter (farad/meter).


CGD0
Real
4e-11
Gate-drain overlap capacitance perimeter (farad/meter).


CGS0
Real
4e-11
Gate-source overlap capacitance perimeter (farad/meter).


CJ
Real
2e-4
Capacitance at zero-bias voltage per square meter of area (farad/meter2).


CJSW
Real
1e-9
Capacitance at zero-bias voltage per meter of perimeter (farad/meter).


FC
Real
0.5
Substrate-junction forward-bias coefficient.


GAMMA
Real
0.526
Body-effect parameter.


IS
SI.Current
1e-14
Reverse saturation current at 300K.


KP
Real
27.6e-6
Transconductance parameter (A/V2).


L
SI.Length
100e-6
Gate length.


LAMBDA
Real
0
Channel length modulation (V-1).


LD
SI.Length
0.8e-6
Lateral diffusion.


MJ
Real
0.5
Bulk junction capacitance grading coefficient.


MJSW
Real
0.33
Perimeter capacitance grading coefficient.


PB
SI.Voltage
0.75
Surface inversion potential.


PD
SI.Length
4e-4
Drain junction perimeter.


PS
SI.Length
4e-4
Source junction perimeter.


RD
SI.Resistance
10
Drain ohmic resistance.


RS
SI.Resistance
10
Source ohmic resistance.


RB
SI.Resistance
10
Bulk ohmic resistance.


RG
SI.Resistance
10
Gate ohmic resistance.


TOX
SI.Length
1e-7
Gate oxide thickness.


VT0
SI.Voltage
1
Zero-bias threshold voltage.


W
SI.Length
100e-6
Gate width.







Variables of interest to the library user




Table 7. Static Model.



Name
Description



vthDC
Threshold voltage.



vdsDC
Drain to source voltage.



vgsDC
Gate to source voltage.



vbsDC
Bulk to source voltage.







Table 8. Large-signal model.



Name
Description



vthTran
Threshold voltage.



vdsTran
Drain to source voltage.



vgsTran
Gate to source voltage.



vbsTran
Bulk to source voltage.






Table 9. Small-signal model.



Name
Description



gate_vAC_Re
Gate voltage. Real part.



gate_vAC_Im
Gate voltage. Imaginary part.



bulk_vAC_Re
Bulk voltage. Real part.



bulk_vAC_Im
Bulk voltage. Imaginary part.







Table 10. Global variables.



Name
Description


scaleGMIN
Scale factor of the GMIN stepping algorithm for bias point calculation.


GMIN
Conductance in parallel with the pn junction.


freq
AC small-signal frequency.


Temp
Temperature.







References


Massobrio, G. and Antognetti, P. (1993): Semiconductor Device Modeling with SPICE.
McGraw-Hill, Inc.

Model's equations can be found in src package documentation.






Parameters




NameDefaultDescription


HIDDEN_COMPONENTfalseEnable or disable log


AD1e-8drain difussion area [m2]


AS1e-8Source difussion area [m2]


CGBO2e-10Gate-bulk overlap capacitance per meter [F/m]


CGDO4e-11Gate-drain overlap capacitance per meter [F/m]


CGSO4e-11Gate-source overlap capacitance per meter [F/m]


CJ2e-4Capacitance at zero-bias voltage per square meter of area [F/m2]


CJSW1e-9Capacitance at zero-bias voltage per meter of perimeter [F/m]


FC0.5Substrate-junction forward-bias coefficient


GAMMA0.526Body-effect parameter [V0.5]


IS1e-14Reverse saturation current at 300K [A]


KP27.6e-6Transconductance parameter [A/V2]


L100e-6Gate length [m]


LAMBDA0.00Channel-length modulation [V-1]


LD0.8e-6Lateral diffusion [m]


MJ0.5Bulk junction capacitnce grading coefficient


MJSW0.33Perimeter capacitance grading coefficient


PD4e-4drain difussion perimeter [m]


PS4e-4source difussion perimeter [m]


PB0.75Junction potencial [V]


PHI0.65Surface inversion potencial [V]


RD10Drain ohmic resistance [Ohm]


RS10Source ohmic resistance [Ohm]


RB10Bulk ohmic resistance [Ohm]


RG10Gate ohmic resistance [Ohm]


TOX1e-7Gate oxide thickness [m]


VTO1Zero-bias threshold voltage [V]


W100e-6Gate width [m]


RSB1e-4Source-Bulk junction resistance [Ohm]


RDB1e-4Drain-Bulk junction resistance [Ohm]




Modelica definition


model Spice2MOS1 
  extends src.BREAKOUT.Spice2MOS1;
end Spice2MOS1;







SPICELib.parts.breakout.Spice2MOS1P
SPICELib.parts.breakout.Spice2MOS1P

SPICELib.parts.breakout.Spice2MOS1P

Information





Spice2MOS1P - SPICE2 Level1 p-channel MOSFET




Figure 1. p-channel MOSFET.




Nodes



Table 1. Instantiations of Pin class.



Name
Description


d
drain node


s
source node


g
gate node


b
bulk node







Table 2. drain node variables.



Name
Description



d.vDC
Static model.



d.vTran
Large-signal voltage.



d.vAC_Re
AC small-signal voltage. Real part.



d.vAC_Im
AC small-signal voltage. Imaginary part.







Table 3. (-) source node variables.



Name
Description



s.vDC
Static model.



s.vTran
Large-signal voltage.



s.vAC_Re
AC small-signal voltage. Real part.



s.vAC_Im
AC small-signal voltage. Imaginary part.







Table 4. (-) gate node variables.



Name
Description



g.vDC
Static model.



g.vTran
Large-signal voltage.



g.vAC_Re
AC small-signal voltage. Real part.



g.vAC_Im
AC small-signal voltage. Imaginary part.






Table 5. (-) bulk node variables.



Name
Description



b.vDC
Static model.



b.vTran
Large-signal voltage.



b.vAC_Re
AC small-signal voltage. Real part.



b.vAC_Im
AC small-signal voltage. Imaginary part.








Parameters



Table 6. p-channel MOSFET parameters.



Name
Type
Default
Description


AD
SI.Area
1e-8
Drain junction area.


AS
SI.Area
1e-8
Source junction area.


CGB0
Real
2e-10
Gate-bulk overlap capacitance perimeter (farad/meter).


CGD0
Real
4e-11
Gate-drain overlap capacitance perimeter (farad/meter).


CGS0
Real
4e-11
Gate-source overlap capacitance perimeter (farad/meter).


CJ
Real
2e-4
Capacitance at zero-bias voltage per square meter of area (farad/meter2).


CJSW
Real
1e-9
Capacitance at zero-bias voltage per meter of perimeter (farad/meter).


FC
Real
0.5
Substrate-junction forward-bias coefficient.


GAMMA
Real
0.526
Body-effect parameter.


IS
SI.Current
1e-14
Reverse saturation current at 300K.


KP
Real
27.6e-6
Transconductance parameter (A/V2).


L
SI.Length
100e-6
Gate length.


LAMBDA
Real
0
Channel length modulation (V-1).


LD
SI.Length
0.8e-6
Lateral diffusion.


MJ
Real
0.5
Bulk junction capacitance grading coefficient.


MJSW
Real
0.33
Perimeter capacitance grading coefficient.


PB
SI.Voltage
0.75
Surface inversion potential.


PD
SI.Length
4e-4
Drain junction perimeter.


PS
SI.Length
4e-4
Source junction perimeter.


RD
SI.Resistance
10
Drain ohmic resistance.


RS
SI.Resistance
10
Source ohmic resistance.


RB
SI.Resistance
10
Bulk ohmic resistance.


RG
SI.Resistance
10
Gate ohmic resistance.


TOX
SI.Length
1e-7
Gate oxide thickness.


VT0
SI.Voltage
-1
Zero-bias threshold voltage.


W
SI.Length
100e-6
Gate width.








Variables of interest to the library user




Table 7. Static Model.



Name
Description



vthDC
Threshold voltage.



vsdDC
Source to drain voltage.



vsgDC
Source to gate voltage.



vsbDC
Source to bulk voltage.







Table 8. Large-signal model.



Name
Description



vthTran
Threshold voltage.



vsdTran
Source to drain voltage.



vsgTran
Source to gate voltage.



vsbTran
Source to bulk voltage.






Table 9. Small-signal model.



Name
Description



gate_vAC_Re
Gate voltage. Real part.



gate_vAC_Im
Gate voltage. Imaginary part.



bulk_vAC_Re
Bulk voltage. Real part.



bulk_vAC_Im
Bulk voltage. Imaginary part.







Table 10. Global variables.



Name
Description


scaleGMIN
Scale factor of the GMIN stepping algorithm for bias point calculation.


GMIN
Conductance in parallel with the pn junction.


freq
AC small-signal frequency.


Temp
Temperature.







References


Massobrio, G. and Antognetti, P. (1993): Semiconductor Device Modeling with SPICE.
McGraw-Hill, Inc.

Model's equations can be found in src package documentation.






Parameters




NameDefaultDescription


HIDDEN_COMPONENTfalseEnable or disable log


AD1e-8drain difussion area [m2]


AS1e-8Source difussion area [m2]


CGBO2e-10Gate-bulk overlap capacitance per meter [F/m]


CGDO4e-11Gate-drain overlap capacitance per meter [F/m]


CGSO4e-11Gate-source overlap capacitance per meter [F/m]


CJ2e-4Capacitance at zero-bias voltage per squere meter of area [F/m2]


CJSW1e-9Capacitance at zero-bias voltage per meter of perimeter [F/m]


FC0.5Substrate-junction forward-bias coefficient


GAMMA0.526Body-effect parameter [V0.5]


IS1e-14Reverse saturation current at 300K [A]


KP27.6e-6Transconductance parameter [A/V2]


L100e-6Gate length [m]


LAMBDA0.00Channel-length modulation [V-1]


LD0.8e-6Lateral diffusion [m]


MJ0.5Bulk junction capacitnce grading coefficient


MJSW0.33Perimeter capacitance grading coefficient


PD4e-4drain difussion perimeter [m]


PS4e-4source difussion perimeter [m]


PB0.75Junction potencial [V]


PHI0.65Surface inversion potencial [V]


RD10Drain ohmic resistance [Ohm]


RS10Source ohmic resistance [Ohm]


RB10Bulk ohmic resistance [Ohm]


RG10Gate ohmic resistance [Ohm]


TOX1e-7Gate oxide thickness [m]


VTO-1Zero-bias threshold voltage [V]


W100e-6Gate width [m]


RSB1e-4Source-Bulk junction resistance [Ohm]


RDB1e-4Drain-Bulk junction resistance [Ohm]




Modelica definition


model Spice2MOS1P 
  extends src.BREAKOUT.Spice2MOS1P;
end Spice2MOS1P;





HTML-documentation generated by Dymola Tue Oct 14 18:26:29 2003
.